Plumerai looks to revolutionize the world of AI by making small things intelligent.
We work on the area of hardware acceleration of AI algorithms, our target is to run very complex computations on battery power.
We are looking for talented ambitious FPGA engineer to work on the development of the new generation of Machine Learning accelerators. The work will involve a lot of design exploration and rapid prototyping. Close collaboration with Software and algorithm teams is a part of development process.
This is a fantastic opportunity to learn and contribute about the exciting field of Artificial intelligence.
Architecture, design, verification and validation of RTL components. Board bring-up and debugging.
Cross-team collaboration and customer support.
Challenging and creative environment where contributions are highly visible. Suggestions and taking initiatives are appreciated.
We provide a lot of autonomy and expect our engineers to own the design from A to Z.
We expect our engineers to be energetic and driven to success. This is the opportunity to learn a lot and take on many responsibilities. Career advancement opportunities are to be expected as company grows.
- At least 3 years of experience in similar role.
- Working knowledge and experience with modern FPGA architectures, CAD tools (Vivado or Quartus) and techniques.
- Knowledge of computer architecture. Understanding of bandwidth and latency optimization techniques.
- RTL and testbench development with VHDL or Verilog.
- Familiarity with SoC architectures is desirable.
- Knowledge of computer arithmetics.
- Experience in hardware acceleration of mathematical algorithms.
- System-level data exchange protocols and interconnects: AXI, AHB or others.
- Good knowledge of hardware verification methodologies.
- Git or similar VCS.
- Scripting and flow automation (bash, Tcl or others.)
- Good spoken and written English.
- Linux and device driver development experience.
- High-speed serial interfaces (Ethernet, PCIe, USB or others).
- Advanced verification techniques (assertions etc.) are desirable.
- Knowledge and/or experience of ASIC design is a plus.
- Knowledge of parallel computing (CUDA, OpenMP) will be a plus.
- Knowledge of ML frameworks (Tensorflow, Pytorch) will be a big plus.
- Flexible working hours
- Research work support
- Paid seminars and conferences trips