Senior FPGA Design Verification Engineer [rekrutacja online]
Miejsce pracy: Kraków
Nr Ref.: 2000000B4S
Nr Ref.: 2000000B4S
Daily activities
As part of our team you will contribute to requirements analysis and decomposition, design and implement the verification scenarios using System Verilog of new FPGA functionalities for 5G telecommunication system following the complete end to end project life cycle.
You will develop extensive knowledge of 5G system physical layer, Nokia hardware platforms and the way our customers are deploying them. You will contribute to develop innovative solutions to address Nokia strategy in the 5G domain and beyond.
We work with:
- System Verilog, UVM
- Git, IDM
- Python,
- Linux
- Testing frameworks
- JIRA
- Version control and code review systems
- Continuous integration systems
Our expectations:
- Education: gained BSC / Engineer in: Telecommunication, Computer Science, Electronics or a similar subject
- Good knowledge of English (both spoken and written)
- FPGA programming - verification skills: System Verilog, UVM
- Experience in FPGA verification or integration (minimum 3 years of commercial experience)
- Matlab/Octave or similar tool knowledge
- Understanding of technical documentation and technical writing skills
- Low level/platform programming & debugging tools knowledge
- Verilog/VHDL knowledge
- Good mathematical skills
- Telecommunication knowledge is an advantage
- Embedded system background knowledge is an advantage
- Good programming skills with script languages (e.g. Python, Perl, Tcl) is an advantage