Verilog Verification Engineer
Work Location: Wrocław
Project description
As a trusted collaborator to one of the biggest silicon manufactures in the industry we have been invited to work on the new generation of DSP cores for ADAS radars used in self driving cars of the future.
First phase of the project focuses mainly on design, modeling and verification of the IP core. Close cooperation with the Logic design team,HW verification team and compiler group is required.
Scope of the second phase will be development of highly optimized linear algebra libraries (BLAS) and integration with neural network framework (Caffe).
You will be responsible for
- Verification of Hardware design
- Writing new tests
- Maintaining and migrating existing ones.
- Close cooperation with logic design team.
Requirements
- At least 1 year of professional experience
- Experience with System Verilog
- Knowledge of UVM (Universal Verification Methodology)
- General knowledge CPU design testing practices
- Good communication skills
- Good spoken and written English
We Offer
- Great working atmosphere in an international team of excellent specialists
- The culture of open communication and exchange of experience, access to the latest technology and our know-how
- Participation in interesting and varied projects (local and international), the possibility of foreign travel
- Development paths suited to individual talents: international exchange of knowledge, professional certifications
- Working conditions that will give you a sense of financial security and will make your dreams come true
- Flexible working time
- A rich benefits package: private medical care, group life insurance, travel insurance, food subsidies, participation in sport classes, cultural activities
- Delicious coffee and 20 different tea flavors
Send you application by clicking "Aplikuj Teraz" button.
Your message subject shall include job position.